Intel StrataFlash Programmer

I finished the programmer for the on-board Intel StrataFlash on my FPGA development board today. It was much more of a hassle than I thought it was going to be. Digilent, maunfacturer my FPGA board, had done a fantastic job on their user manuals on every topic except for the memory resources, which was disappointing. I had to dig my way through a couple datasheets before I got all the information I needed to operate the Flash device.

Coding Has Begun

I began coding certain elements of the OZ-3 in the last couple of weeks. It’s been going alright; I had to look back at my Logisim schematics to remember just how some parts work! I coded the smaller components, such as generic falling- and rising-edge triggered registers that can be sized according to their purpose. Also, I’ve done the ALU and condition block. Unfortunately, since I made up the schematics, I’ve forgotten the reasons behind various buffers that keep everything timed correctly (i.e., an instruction’s data doesn’t get to a stage in the pipeline too soon). This caused confusion on my part when programmed these buffers into the EX and WB stages.

Test CPU 1 – FPGA Implementation

As I mentioned in my previous post, the next step that I wanted to take after designing the OZ-3 in simulation was to design and implement a simple CPU in an FPGA, just to get used to complex systems. Ironically, a couple days before I made that post, I had finished that CPU. It’s called Test CPU 1.

I said “simple CPU,” and by that, I mean a single-cycle, 16-bit RISC. The instruction set is ten instructions total; only the essentials. It doesn’t have any input capabilities, and all output capabilities are in 32 individual output pins, so data transfers would be rather difficult. Also, there are eight 16-bit registers. It can address 256 bytes of dRAM, and programs are limited to 4 MB, organized as 2Mbits x 16bits. The ALU is capable of addition and subtraction only, and it can only branch on zero. Here’s the full instruction set:

The OZ-3

Because I’m starting this blog so late in this processor’s development, I figured I would give a summary of what it is and what stage of design it’s in.

It official terms, the OZ-3 is a 32-bit, 5-stage RISC (reduced instruction set computer). This means that it can operate on 32-bit values, it has a small instruction set of basic instructions, can address four gigabytes of memory, and instructions move through five stages within the processor. It also has 32 registers, with r0 hardwired to 0. The stages are as follows:

• Instruction Fetch (IF)
• Instruction Decode (ID)
• Execute (EX)
• Memory and Input/Output (MEMIO)
• Writeback (WB)

Hello world!

I’m going to be using this blog essentially to document and record the development of a processor I’ve designed: the OZ-3. I’ve run it at gate-level simulation, and the next step I want to take is an FPGA implementation. After that, I would really, really like to build my processor out of individual ICs, like computers from way back when. I think it’d be pretty cool to get that close to the processor in a real-world implementation.

I’ve been inspired to do this project mainly by myself, if that doesn’t sound too pretentious. The story of my interest in computer engineering goes back aways, but it’d make sense if I explained it. Other things that got me going were other homebrew CPU projects online, such as BMOW and Magic-1. You ought to Google them, they’re really quite fascinating.

For the interested, I’ll include a (lengthy) story of how I got into computer engineering.